This invention relates to a data processing system which is controlled by a microprogram and which includes two control processors connected in dual fashion.
It has been strongly desired that data processing systems should be more and more reliable. Generally a data processing system is provided with various memory apparata such as a main memory, a cache memory and a control store. The data processing system is further provided with a central processing unit including typically a control store, a control processor and a cache. The control processor reads microinstructions from the control store and operands from the main memory or cache memory, thereby to process arithmetically the operands under control of the microinstructions. The reliability of these memory apparata has been much improved by using an error detection and automatic correction circuit (hereinafter called "EDAC circuit").
If the whole data processing system is constructed in dual fashion, the system will be much more reliable, but its cost will be raised considerably. In a data processing system with only one control processor, microinstructions cannot be executed if the control processor experiences a fault. Until it is repaired, the control processor cannot carry out arithmetic operations. Availability of the whole system is thus reduced. Faults, if any, of the control processor occur in, for example, a micro-address output, a main memory interface output or an input data bus. But it is very troublesome and time-consuming to detect where in the control processor the faults have occurred because faults can take place at various parts of the control processor.